GitHub

PicoRV32 - A Size-Optimized RISC-V CPU

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt ...
IEEE

Verilog Code Generation of Hierarchical Design Using LLMs

Abstract: Creating RTL hierarchy and generating module-by-module Verilog code, both through a large language model (LLM), are presented. (1) For RTL hierarchy, LLM is prompted to identify a list of ...
Nature

Signal averaging in cryogenic fast-field-cycling NMR experiments

The subject of nuclear magnetic resonance (NMR) relaxometry is the dependence of the nuclear spin-lattice relaxation time constant \(T_1\) on magnetic field and temperature 1. Relaxation frequently is ...
CNX Software

AERIS-10 open-source hardware radar can track multiple objects up to 20km away

AERIS-10 is an open-source hardware, “low-cost” (more on that later) 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation and based on an AMD Artix-7 FPGA.
IEEE

Generation of Synthesizable Verilog Code From Natural Language Specifications

Abstract: This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language ...
Design-Reuse

Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach

In today’s fast-paced silicon industry, hardware design is under constant pressure to innovate, iterate, and ship faster. Traditional Register Transfer Level (RTL) design processes—though foundational ...
elektormagazine

Learn FPGAs and Verilog with Elektor Academy Pro

Explore FPGA development using Verilog with this complete kit from Elektor Academy Pro, including hardware, structured learning and practical signal processing projects. Discover an exciting new ...
Semiconductor Engineering

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)

A new technical paper titled “VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation” was published by researchers at the University of Florida.
Nature

FPGA-based CCD signal acquisition and transmission system design

The spectrometer is an optical device that employs the principle of light dispersion to decompose the complex compositions of light to form a spectrum. It finds applications in various fields of ...
LinkedIn

Race Conditions and How to Prevent Them in Verilog

Race conditions are a type of concurrency-related bug that arises when two or more processes attempt to update the same variable or register simultaneously, and the final outcome depends on the ...